Performance Evaluation Of 10T SRAM Cell Using Adiabatic Pre-Charged Unit Cell

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P. Chaitanya, K.Srinivas Rao, M. Ravi Kumar, Chella Santhosh


This paper contrasts the performance evaluation of the standard 10T SRAM circuit with that of the Adiabatic 10T SRAM. There is a strong degree of adiabatic SRAM power reduction. The same SRAM technology is explored through the use of the above methodology. For both SRAM, certain parameters are often measured such as the average power, rise time, fall time, Delay etc. Our effort to recycle energy contained in the parts and in the cells and reused it via a phenomenal energy recovery strategy named adiabatic concepts. As this adiabatic driver is added, the energy decrease on the ground would be minimized to a greater extent during the SRAM "1 to 0" transformation. The TANNER EDA simulates all the desired parameters. Modernization and the need for computer applications, anywhere they can be transmitted, contribute to an ever-growing need for lightweight, inexpensive, secure and low power battery powered handheld devices. A robust adiabatic SRAM is established in this paper. The key target is to use adiabatic circuits to compensate for a loss of the output in order to obtain a medium performance for SRAM. Adiabatic switching concepts are used to construct the planned architecture.

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