Random Testing of 3-cell NPSF in memories using LFSR and NLFSR

Abstract

This paper proposes a new check analysis method for testing of NPSF defects in wide range access memories. LFSR and NLFSR’s are used as address generators to select a particular cell in the memory. Single bit change sequences are used as a test patterns to find the active faults. It has one fault cell and two forced unit. It is used to perceive the ANPSF impact on base cell by way of switching of patterns in the corresponding deleted neighborhood cells. The whole ANPSF ideal structure for memory testing is advanced the use of Verilog HDL. The random testing method gives the better performance than the conventional methods. The testing method is implemented using Vivado 14.7 and Nexys four DDR Artix 7 FPGAboard.