Low power High Speed Design of 4BIT Ripple Carry adder using Domino logic

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lanka Kiran Kumar, Dr. Samiran Chatterjee, J.Sunilkumar


Accurate domino logic circuit keeper control can enlarge the performance, speed. Although, keeper feedback circuit is correlated with the positive feedback gain excessively delay variability is expanded. The main aim is to decrease the delay and reduce the loop gain effect, here domino clock delayed dual keeper (CDDK) circuit is conferred .During the commencing estimation phase, disabled the two keeper devices of the keeper circuit in CDDK domino structure. By decreasing the dispute current concurrently the circuit speed of operation is intensified. The carried out various metrics and outcomes are analyzed for the circuit simulations .Moreover , the simulations are accomplished on a 4-bit ripple adder using structure of CDDK demonstrate decreased characteristics of delay variability due to the domino CDDK structure smaller loop gain in opposition of domino circuit The demonstration of intensified by  turn down variance current. Through the counterpart of domino logic circuits in opposition of comparison outcomes are validated. By using this tanner power consumption is around 8 micro watts. The analyzing of circuits is carried out using standard CMOS tanner tool using library of 45nm technology.

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