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The LFSRs have been employed as test pattern generator in BIST for decades; however an emerging problem with design constraints leads a lot of improvements in this field. This paper presents a memory efficient FSM encoding-based method to generate test patterns for a given primitive polynomial LFSR TPG. Here test patterns generated from LFSR is divided into groups and follows encoding to transform into multiple test patterns. These newly generated encoded test patterns further divided into transitional and non- transitional blocks which control the bit transitions over encoded values. This weighted driven bit transition also prevents certain bit transitions that reduce the dynamic power as well during testing process. Here highly optimized LFSR test pattern generation is accomplished with high performance TPG design. Extra clocking is also applied to control LFSR output test pattern for improved randomization characteristics of test patterns and pseudorandom measures. The generated random patterns from LFSR are applied to CUT for improved fault coverage using shift and scan method.
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