Design and Analysis of Low Power High Speed Sense Amplifier for Memory Application

Abstract

Sense amplifiers are extensively used in memory. Sense amplifiers are one of themost vital circuits in the periphery of CMOS memories. We know that memory is the heart ofall digital systems. Today all worlds are demanding high speed and low power dissipation aswell as small area. We know that speed and power dissipation of memory is overall dependsupon thesenseamplifierweused and theirperformancestronglyaffects both memoryaccess time, and overall memory power dissipation.   So it is important to design a goodsense amplifier which performs well in both speed and power dissipation. In this dissertation,an implementation of a most efficient sense amplifier is done by comparing the best knownsense amplifier in today.The dissertation focuses on design, simulation and performanceanalysis ofsenseamplifiers.

In this paper, current latch sense amplifier and body bias controlled current latch senseamplifier are designed and results compared. The result shows that the body bias controlledcurrentlatchsenseamplifierisperformingbest.Theresultalsoshowsanovelsenseamplifier which consumes small power at same time its speed is faster than other senseamplifiers.

Allthedesignshavebeenimplemented,synthesisandsimulatedon180nmCMOStechnology usingtanner tool version16.1.