Design and Comparision of 16X16 Reversible Vedic Multiplier using Different Adders

Abstract

In this paper we have designed and analyzed 16-bit Vedic Multiplier using Ripple Carry Adder(RCA) , Carry Look- Ahead Adder(CLA) and Carry Select Adder(CSA). The design was simulated using Xilinx ISE design suite 14.7 and ModelSim 6.3g . The area and speed of the Reversible Vedic Multiplier using different Adders are compared. Carry Look Ahead Adder with a different architecture having less number of Reversible Logic Gates and garbage outputs are designed.