Design of Parallel Memory Allocation using Error Resilient Ternary Content­addressable Memory for Fast Error Correction

Abstract

This article addresses the implementation of error resilient ternary content-addressable memory (ER-TCAM) based parallel memory allocation (PMA) systems with error resilient properties, which can capable of detecting and correcting the errors during the parallel data allocation. This technique uses simple, single-bit parity for fault detection which has a minimal critical path overhead. Synchronization issues generated during the parallel read, write operations are effectively minimized by using the priority circuit with crossbar switching. Further, the concept of PMA is implemented through data transfer between main memory to slave devices and vice­versa. The simulation results shows that the proposed ER-TCAM based PMA resulted in superior performance as compared to the conventional approaches.