Evaluate of Stand by Leakage current in CMOS Circuits by Sleepy methodology

Abstract

In the CMOS based VLSI circuits technology scaling is done towards down due to its size and for achieving higher operating speed. As we know that leakage power consumption of current in CMOS technology is a great challenge.  We have also considered size, leakage power, average power & speed of operation (delay) in such a way so that we can control the leakage current. The sub threshold voltage is declining in successive nanometer technologies and has an associated effect of enhanced leakage current. We have also studied previous techniques in which the leakage power increases in an integrated circuit. Because transistors leak even when they are not activated and significant power dissipation takes place even during inactive state of circuits. The sleepy technique provides maximum leakage current reduction with lower output levels. The proposed circuit technique has been applied to some inverters and the result has been compared with earlier inverter leakage minimization techniques. All low leakage models of inverters are designed and simulated in Tanner Tool technology.